1. Field of the Invention
The present invention relates to an electrical fuse circuit, a memory device and an electronic part.
2. Description of the Related Art
FIG. 16 is a view showing a semiconductor memory chip including a laser fuse. The semiconductor memories in recent years include a redundant memory cell using a laser fuse, in which a defective memory cell is replaced with a redundant memory cell in general. The laser fuse is a nonvolatile ROM cutting a wiring layer with a laser beam to write (for example, in an uncut state, it is in an electrically connected state being “0 (zero)”, and in a cut state, it is in an electrically unconnected state being “1”), and the replacement to the redundant memory cell is performed by letting this ROM memorize the address of the defective memory cell. However, after a memory chip 1601 using the laser fuse is packaged in a package 1602, no laser LS is emmittable thereto. It is known as a phenomenon that a DRAM in the memory chip 1601 is degraded in refresh characteristic and the like, affected by heat or the like at the time of the packaging. However, it is impossible to emit the laser LS thereto after the packaging. Therefore, a method, in which an electrically writable electrical fuse is used as a nonvolatile ROM and the ROM is made to memorize the address of the defective memory cell to replace the defective memory cell with the redundant memory cell, is under study.
FIG. 17 is a view showing a configuration example of an electrical fuse circuit. Hereinafter, a field-effect transistor is simply called a transistor. An electrical fuse capacitor 101 is connected to between a voltage VRR and a node n3. An n-channel transistor 102 is a protection transistor connected to a voltage VPP with a gate thereof, to the node n3 with a drain thereof, and to a node n2 with a source thereof. The voltage VPP is for example 3V. An n-channel transistor 103 is a write circuit connected to a write signal WRT with a gate thereof, to the node n2 with a drain thereof, and to a ground with a source thereof.
Subsequently, the description will be given of the configuration of a read circuit 110. An n-channel transistor 111 is connected to a read signal RD with a gate thereof, to the node n2 with a drain thereof, and to a node n4 with a source thereof. An n-channel transistor 113 is connected to a node n5 with a gate thereof, to the node n4 with a drain thereof, and to a ground via a resistance 114 with a source thereof. A p-channel transistor 112 is connected to the node n5 with a gate thereof, to a voltage VII with a source thereof, and to the node n4 with a drain thereof. The voltage VII is for example 1.6 V. A nonconjunction (NAND) circuit 115 is connected to a power supply voltage VII and an input terminal thereof is connected to the node n4 and the line of a signal RSTb, and an output terminal thereof is connected to the node n5. A NOT circuit 116 is connected to the node n5 with an input terminal thereof and to the line of a signal EFA with an output terminal thereof.
FIG. 18 is a view showing a configuration example of an electrical fuse circuit 215 and a peripheral circuit thereof and FIG. 19 is a timing chart showing an example write operation of an electrical fuse circuit. The electrical fuse circuit 215 corresponds to the electrical fuse circuit in FIG. 17. A booster circuit & level control circuit 201 boosts the voltage and controls the level to supply the voltage to a plurality of unit circuits 203. An electrical fuse control circuit 202 outputs the signal RD, the signal RSTb, a signal EF-WRITE, a signal EF-START, a signal EF-CLK, a signal EF-STRB to the plurality of unit circuits 203. Each of the unit circuits 203 includes flip-flops (FFs) 211, 212, a NAND circuit 213, and a NOT circuit 214 and an electrical fuse circuit 215. The flip-flops 211 in the plurality of unit circuits 203 input address signals A0 (zero) to A2 and a valid signal VALID and compose address resistors 204, respectively. For convenience's purpose of description, the case of 3-bit address signals A0 (zero) to A2 is described as an example. The valid signal VALID is a signal indicating whether or not to validate memorized contents of the electrical fuses corresponding to the address signals A0 (zero) to A2. For instance, when no defective memory cell exists and no replacement to the redundant memory cell is required, just make the valid signal VALID to low level. The flip-flops 212 in the plurality of unit circuits 203 compose shift resistors 205.
Before a time t1, the pulse of the signal EF-STRB is inputted into clock terminals of the flip-flops 211 and the address signals A0 (zero) to A22 are inputted into the input terminals of the flip-flops 211, respectively.
The description will be given of a writing example in the case where the signals such as the address signal A0 (zero) at low level, the address signal A1 at high level, the address signal A2 at low level, and the valid signal VALID at high level, as an example, are written into the electrical fuse. The register 211 of the address signal A0 (zero) outputs low level. The register 211 of the address signal A1 outputs high level. The register 211 of the address signal A2 outputs low level. The register 211 of the valid signal VALID outputs high level.
At and after the time t1, a clock signal CLK becomes a clock pulse having a constant frequency. The signal EF-WRITE is a pulse having the same cycle as of the clock EF-CLK. At the time t1, the start signal EF-START is turned from high level into low level. Then, the shift resister 212 shifts the start signal EF-START to output it to the next shift register 212. With this, the resister 212 of the address signal A0 (zero), the resister 212 of the address signal A1, the resister 212 of the address signal A2 and the resister 212 of the valid signal VALID output the shifted pulse, respectively.
After the time t1, the NOT circuit 214 of the address signal A0 (zero) keeps low level to output no pulse as a write signal WRT. After the time t2, the NOT circuit 214 of the address signal A1 outputs a high-level pulse as a write signal WRT. After the time t3, the NOT circuit 214 of the address signal A2 keeps low level to output no pulse as a write signal WRT. After the time t4, the NOT circuit 214 of the valid signal VALID outputs a high-level pulse as a write signal WRT.
In FIG. 17, when the write signal WRT becomes high level, the transistor 103 is turned on. The high voltage VRR (for example, 8V) is applied to the capacitor 101. The electrical fuse is composed of the capacitor 101, and is in the electrically unconnected state when nothing is done. When the high voltage (for example, 8V) is applied to both the terminals of the capacitor 101, an insulating film of the capacitor 103 is broken so that the capacitor is put into the electrically connected state. These two states are assigned to data 0 (zero) and data 1, respectively. For example, when it is in the electrically unconnected state where the insulating film of the capacitor is not broken, “0 (zero)” is assigned, and when it is in the electrically connected state where the insulating film of the capacitor is broken, “1” is assigned. The capacitor 101 can be used as a nonvolatile ROM.
The high voltage required to perform a breaking operation of the insulating film of the electrical fuse (hereinafter called the “write operation”) is generated by the booster circuit 201 provided in the semiconductor chip. Further, when trying to write into the plurality of capacitors 101 at a time as a write operation, huge current may flow, so that the writing is performed to the capacitors on the one by one basis by providing the shift registers 205.
The description will be given of the write operation into the capacitor (electrical fuse) 101. First, the booster circuit 201 boosts the voltage VRR at the common node of the plurality of capacitors 101 to high voltage (for example, 8V). At this time, the other terminal node n3 of the capacitor is in the floating state, so that the potential of the node n3 increase as well. In this state, the difference between the potentials of both the terminals of the capacitor 101 is still small. After that, the transistor 103 into which the write signal WRT selected by the shift resistor 205 is written is turn on and the high voltage is applied to between both the terminals of the capacitor 101 using the node n3 as a ground to break the insulating film of the capacitor 101. At this time, in the capacitor 101 corresponding to the unselected write signal WRT, the node n3 is still in the floating state, so that the high voltage is not applied to between both the terminals of the unselected capacitor 101. Should the high voltage be applied, the insulating film of the capacitor into which the writing is not intended to be performed actually, will be broken.
FIG. 20 is a timing chart of the semiconductor memory chip including the electrical fuse circuit when the power supply starts. A power supply voltage VDD is the power supply voltage for the semiconductor memory chip, and is for example 1.8 V. With the power supply starting, the voltages VDD, VRR and RC increase gradually. After a while, the voltage VRR keeps around 1.6 V. The signal RSTb keeps low level. In FIG. 17, when the signal RSTb is low level, the node n5 becomes high level. Then, the transistor 112 is turned off and the transistor 113 is turned on. As a result, the node n4 turns from the floating state into low level. After that, the signal RSTb turns from low level into high level. When the capacitor 101 is in the connected state, the node n4 becomes high level and the output signal EFA becomes high level. Meanwhile, when the capacitor 101 is in the unconnected state, the node n4 becomes low level and the output signal EFA becomes low level. After that, the voltage VRR and the read signal RD becomes the ground, the transistor 111 turns off, and the output signal EFA is kept. Based on the above operation, the read circuit 110 outputs the state of the capacitor 101 as a signal EFA.
In Japanese Patent Application Laid-Open No. 2006-147651 (Patent document 1), there is described a semiconductor integrated circuit, in which, a fuse metal being unconnected by being applied Vdd to one end portion thereof and at the same time by being applied a laser beam is provided above a semiconductor substrate with the other end portion thereof being provided on the substrate, and the fuse metal is electrically connected to a drain of an N-channel transistor for programming being applied Vss as a back bias.
Also, in Japanese Patent Application Laid-Open No. Hei9-185897 (Patent document 2), there is described a redundant fuse circuit including: a node determining a logic state of a redundant addressing signal, a fuse provided in parallel with the node, and a precharge circuit precharging the node in accordance with a clock.
FIG. 21 is a timing chart showing an example writing malfunction of a fuse circuit, which corresponds to FIG. 19. The description of the same signals as in FIG. 19 will be omitted here. In the voltage VRR, a pulse of 8V is generated at the same cycle as of the signal EF-WRITE. When the write operation writing into the plurality of capacitors (electrical fuses) 101 on the one by one basis is repeated, the potential of the node n3 in the unselected electrical fuse circuit downs gradually due to a junction leakage or the like. When the number of the entire bits of the electrical fuse is large, a high voltage 2101 is caused to be applied to both the ends of the capacitor 101 of the unselected electrical fuse, and thereby the writing is caused to be performed into the capacitor which is not intended to be written actually, leaving a problem.